The present invention relates generally to interprocessor communications protocols, and, more specifically, to an asynchronous RS232-compatible interprocessor communications protocol used between a master control processor and a slave processor for use in consumer electronic products.
Many consumer electronic products use a microprocessor chip to control the features and operation of the product. Such products include, for example, but are not limited to, audio and/or video cassette players and/or recorders, receivers, telephone answering devices, photocopying machines, television sets, compact disc players, and facsimile machines. Most of these products include a user interface comprised of a keyboard or pad and an information display to allow a user to select any of a number of desired operations possible and to view the status of the product at any particular moment. Typically, these products perform a multitude of functions or process a large amount of data. To handle all the functions and processing capabilities demanded of a product, sophisticated processors are required.
Ideally, a single control processor is used to control all the functions of the product; however, many products have a large number of input or output functions, or both, with many external interrupts with which to be interfaced. For example, a new upcoming digital cassette deck, better known as the digital compact cassette ("DCC") deck, has the ability digitally to record and play back audio information, as well as play back analog compact cassettes. To process the digital information, the control processor must handle over 1800 bytes of synchronous data, including auxiliary data, system information and digital signal processing status every second at a one megabits per second (Mbits/sec) baud rate. In addition, the DCC deck is required to service an American Electronics Society-European Broadcast Union (AES/EBU) standard bus with up to 96 bytes of "Q" subcode data and 2 bytes of "C" data from a digital source such as a CD player every 13 ms (the CO transmits the "Q" subcode data at a 75 Hz frame rate, while trying to sample and debounce at least 23 keys and scan the display simultaneously. Furthermore, the DCC deck uses a fluorescent indicator panel with 16.times.18 (288 total) segments, which panel further taxes the control processor's abilities.
Control processors capable of all of the above functions are very expensive, too expensive for all but the high-end consumer market. Accordingly, most consumer products, such as the DCC deck above, use multiple processors to perform all the desired functions. These processors include a control processor, which controls the functions of the deck and all other processors, an interface processor, which is used to control the function of the keyboard and display, and other processors for digital signal processing.
To communicate among processors, a communications protocol must be adopted that is efficient, accurate, and fast. One type of communications software made specifically for use with DCC decks is found in AR350 Deck Controller by Phillips, the original developer of the DCC technology. The protocol is a RS232 serial communications protocol used to control the AR350 cassette deck. The protocol follows UART standards, utilizing an eight-bit data, one start and one stop bit format, running at 9600 baud. Furthermore, there are eleven (11) basic control commands with one status byte, which is returned to the host processor. The status byte allows for only one of eight bits to be set at a time, reflecting its current mode of operation. Error correction is performed by sending each command at least three times. To over come the inherent delay of sending three commands, the system attempts to compensate by sending the commands at a higher baud rate than used by other protocols.
A second communications protocol is used in the LR3715M Remote Control Transmitter, manufactured by SHARP. The transmitter uses a Pulse Position Modulation ("PPM") scheme to transmit up to 56 different commands with a six-bit code embedded within a 15-bit data word. The protocol uses an error prevention encoding scheme that requires two 15-bit data words to be transmitted in succession, where the former contains the six-bit code word and the latter provides an inverted form of the six-bit code word. Therefore, the LR3715M system requires at least 30 bits of information to generate one command. Although the cost of semiconductor chips have dramatically fallen over the years, conventional memory and processor chips are still expensive, meaning using 30 bits of data to transmit but a single command is inefficient and expensive.
Accordingly, what is needed is a communications protocol for an electronic system using more than one processor to allow the processors to communicate with each other more efficiently, more accurately, and more quickly than presently available while requiring less effort, less storage space, and/or less demanding error protection means than presently required.